One circuit, two hardware languages
VHDL, short for VHSIC hardware description language, is the second common language for describing a digital circuit. Verilog is the first. They describe the same gates and flip-flops in different words.
Teams choose one for their tools or their history, so an engineer is expected to read both. If you can write a circuit in one, the other is mostly a change of spelling.
By the end of this lesson
Note
I can write the same circuit in VHDL and say how the two languages differ.
Key words
| Word | What it means | Example |
|---|---|---|
| Entity | the VHDL box: its name and its ports | |
| Architecture | the VHDL inside of an entity | |
| Port | one input or output of a circuit | a : in std_logic |
| std_logic | the usual one-bit type in VHDL | |
| Analyse | read and check the source files | |
| Elaborate | build a runnable simulation from them |
The cells students fill in are left blank in this preview.
VHDL separates the box from its insides
Verilog keeps the ports and the logic in one module. VHDL splits them. The entity lists the ports. The architecture says what is inside.
Every port has a direction and a type. The usual type is std_logic, which lives in the ieee library, so the file starts by asking for it. A signal is set with <=.
The half adder in Verilog
// Verilog: one module holds the ports and the logic.
module half_adder(input a, input b, output sum, output carry);
assign sum = a ^ b;
assign carry = a & b;
endmodule
The half adder in VHDL
-- VHDL: the entity is the box, the architecture is inside it.
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (a, b : in std_logic; sum, carry : out std_logic);
end entity;
architecture rtl of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end architecture;
GHDL runs a VHDL design in three steps
The tool is GHDL. ghdl -a analyses the files: it reads and checks them. ghdl -e elaborates the testbench, which builds a program with the same name. ghdl -r runs it.
The Runs below make a folder, write the alarm circuit of lesson 1 in VHDL with a testbench, and take those three steps. Eight lines come out, one for each row, ten nanoseconds apart.
Make a scratch folder
mkdir -p /tmp/vhShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Go into it
cd /tmp/vhShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Write the alarm in VHDL
echo "library ieee; use ieee.std_logic_1164.all; entity alarm is port (door, window, off : in std_logic; siren : out std_logic); end entity; architecture rtl of alarm is begin siren <= (door or window) and not off; end architecture;" > alarm.vhdShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Write its testbench
echo "library ieee; use ieee.std_logic_1164.all; entity alarm_tb is end entity; architecture sim of alarm_tb is signal door, window, off, siren : std_logic := '0'; begin dut: entity work.alarm port map (door => door, window => window, off => off, siren => siren); process begin for i in 0 to 7 loop door <= '0'; window <= '0'; off <= '0'; if i >= 4 then door <= '1'; end if; if (i / 2) mod 2 = 1 then window <= '1'; end if; if i mod 2 = 1 then off <= '1'; end if; wait for 10 ns; report \"door=\" & std_logic'image(door) & \" window=\" & std_logic'image(window) & \" off=\" & std_logic'image(off) & \" siren=\" & std_logic'image(siren); end loop; wait; end process; end architecture;" > alarm_tb.vhdShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Step one: analyse
ghdl -a alarm.vhd alarm_tb.vhdShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Step two: elaborate
ghdl -e alarm_tbShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Step three: run
ghdl -r alarm_tbShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Worked example: Verilog beside VHDL
| Idea | Verilog | VHDL |
|---|---|---|
| A circuit | module | entity and architecture |
| A wire follows an expression | assign y = a & b; | y <= a and b; |
| The operators | & | ^ ~ | and or xor not |
| Capital letters | They matter | They do not |
| Running a testbench | iverilog, then vvp | ghdl -a, -e and -r |
The cells students fill in are left blank in this preview.
A common mistake
Warning
Many people think a and b or c works in VHDL as it does in Verilog. GHDL refuses it: only one kind of logical operator may be combined without brackets. Write (a and b) or c. Brackets also make the meaning clear to the next reader.