How many gates does a design need?
Synthesis is the step that turns a hardware description into a netlist, a list of logic gates and flip-flops joined together. The number of gates is the size of the chip, and its cost.
Two designs can do exactly the same job and need a different number of gates. A tool called yosys counts them for you.
By the end of this lesson
Note
I can say why one design needs fewer gates, and why a latch is a mistake.
Key words
| Word | What it means |
|---|---|
| Synthesis | turning a description into gates |
| Netlist | the list of gates and how they connect |
| Cell | one gate or one flip-flop in a netlist |
| Latch | a part that holds a value while it is enabled |
| Flip-flop | a part that stores a bit at a clock edge |
| yosys | the open source tool that synthesises Verilog |
The cells students fill in are left blank in this preview.
Synthesis turns code into a netlist of cells
A simulator only pretends to be the circuit. Synthesis builds the real thing on paper: a netlist of cells, each one a gate or a flip-flop.
hdl gates FILE TOP is the lab's helper. It runs yosys on a Verilog file and prints how many cells it made and of which kind. TOP is the name of the module to build. The next four Runs write two designs of the same function into /tmp and count them.
Write the first design
echo 'module vote_a(input a, input b, input c, output y); assign y = (a & b) | (a & c); endmodule' > /tmp/vote_a.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Count its gates
hdl gates /tmp/vote_a.v vote_aShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Write the second design
echo 'module vote_b(input a, input b, input c, output y); assign y = a & (b | c); endmodule' > /tmp/vote_b.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Count its gates
hdl gates /tmp/vote_b.v vote_bShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Worked example: one function, two sizes
| Design | Expression | Cells yosys made |
|---|---|---|
| vote_a | (a & b) | (a & c) | 3: two $_AND_ and one $_OR_ |
| vote_b | a & (b | c) | 2: one $_NOR_ and one $_ANDNOT_ |
The cells students fill in are left blank in this preview.
Sharing a factor saves a gate
In vote_a, a is ANDed twice, once with b and once with c. In vote_b, b and c are combined first and a is applied once. That is the same trick as writing a(b + c) instead of ab + ac in algebra.
The cell kinds are yosys's own. $_ANDNOT_ is a AND NOT b, and $_NOR_ is NOT of OR. Some operations cost nothing: x * 2 and x << 1 are only wires moved one place.
Counting by hand in Python
# Count the gates of two ways to write the same function, by hand.
# A gate is one operator: and, or, not.
way_a = ["a and b", "a and c", "or"]
way_b = ["b or c", "a and that"]
print("way a uses", len(way_a), "gates")
print("way b uses", len(way_b), "gates")
# Add a third way, "a and (b or c) and 1", and decide if the 1 costs a gate.
A missing case makes a latch
If a circuit has an output and one case says nothing about it, the circuit must remember the old value. Yosys then builds a latch.
A latch follows its input while it is enabled and holds it afterwards, with no clock edge. Timing tools cannot check it easily, so a latch you did not mean is a bug. A flip-flop stores at a clock edge. The two Runs below write each and count them.
Write a design with a missing case
echo 'module hold(input en, input d, output reg q); always @(*) if (en) q = d; endmodule' > /tmp/hold.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Count its cells
hdl gates /tmp/hold.v holdShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Write a clocked register
echo 'module reg1(input clk, input d, output reg q); always @(posedge clk) q <= d; endmodule' > /tmp/reg1.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Count its cells
hdl gates /tmp/reg1.v reg1Shown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
A common mistake
Warning
Many people think a missing else is harmless, so the output simply stays 0. In hardware, no value is not 0. It means keep the old value, and that needs a latch. Give every output a value in every case.