A siren with two reasons to sound
A truth table lists every possible input of a circuit and the output each one gives. A logic gate is the small circuit that makes one row of it true or false.
A shop alarm should sound if the door or the window opens, unless the owner has switched it off. That rule is three inputs and one output, and you can write it down as a table before anyone builds it.
By the end of this lesson
Note
I can read a truth table and write the gate that makes it.
Key words
| Word | What it means | Example |
|---|---|---|
| Bit | a value that is 0 or 1 | |
| Logic gate | a tiny circuit that turns bits into one bit | AND |
| Truth table | every input pattern with the output it gives | |
| Module | one circuit, with inputs and outputs | |
| Testbench | a module that feeds a circuit and prints what comes out | |
| Simulation | running a circuit description on a computer |
The cells students fill in are left blank in this preview.
A logic gate turns bits into one bit
A logic gate has one or two inputs and one output. Every input and the output is a bit.
An AND gate gives 1 only when both inputs are 1. An OR gate gives 1 when at least one input is 1. An XOR gate, short for exclusive or, gives 1 when the two inputs differ.
Worked example: AND, OR and XOR
| a | b | a AND b | a OR b | a XOR b |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 |
The cells students fill in are left blank in this preview.
A truth table lists every pattern
One input has two patterns, 0 and 1. Two inputs have four. Three inputs have eight, because each new input doubles the rows.
The alarm has three inputs: door, window and off. Its table has eight rows. The next four Runs write the alarm as a module in Verilog, write a testbench for it, and print the table by simulation. The files go in /tmp, so your own lab files stay as they were.
Write the alarm circuit
echo 'module alarm(input door, input window, input off, output siren); assign siren = (door | window) & ~off; endmodule' > /tmp/alarm.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Write its testbench
echo 'module alarm_tb; reg door, window, off; wire siren; integer i; alarm dut(door, window, off, siren); initial begin $display("door window off | siren"); for (i = 0; i < 8; i = i + 1) begin {door, window, off} = i; #1 $display(" %b %b %b | %b", door, window, off, siren); end end endmodule' > /tmp/alarm_tb.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Compile both files
iverilog -o /tmp/alarm /tmp/alarm.v /tmp/alarm_tb.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Run the simulation
vvp /tmp/alarmShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Verilog writes a gate as an operator
The line assign siren = (door | window) & ~off; is the whole circuit. | is OR, & is AND, ^ is XOR and ~ is NOT, which flips a bit.
assign joins a wire to an expression, and the wire follows its inputs at every moment. It is not a step that runs once.
The same table, worked in Python
# Print the truth table of a rule with three inputs.
for door in [0, 1]:
for window in [0, 1]:
for off in [0, 1]:
siren = (door or window) and not off
print(door, window, off, "->", int(siren))
# Change the rule: make the siren sound only when door and window are both 1.
A common mistake
Warning
Many people think OR means one or the other, so 1 OR 1 gives 0. That is XOR. OR gives 1 when at least one input is 1, and that includes both. Check the last row of the table before you trust a gate.
Going further
Change the alarm so the siren also sounds when off is 1 but the door and window are both open.
Write the new truth table by hand first. Then change the assign line in a copy of the file and compare the simulation with your table.