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Free module

Digital design with Verilog and VHDL

Learn digital design hands on: logic gates, adders, clocked counters, waveforms, Verilog, VHDL and gate counts with yosys.

6 lessons330 min lessonCore computer science

The lessons

Each lesson is free to read in full. Create a free account to run its commands in a live lab and to sit its quizzes and tasks.

  1. 1 · Virtual machine lab

    Truth tables and logic gates

    I can read a truth table and write the gate that makes it.

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  2. 2 · Virtual machine lab

    Half adders and full adders

    I can build a full adder from two half adders.

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  3. 3 · Virtual machine lab

    Clocks, flip-flops and counters in Verilog

    I can describe a counter that changes on a clock edge.

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  4. 4 · Virtual machine lab

    Reading a waveform (VCD file)

    I can read a waveform file and say what happened at each clock.

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  5. 5 · Virtual machine lab

    VHDL and Verilog compared

    I can write the same circuit in VHDL and say how the two languages differ.

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  6. 6 · Virtual machine lab

    Counting logic gates with yosys

    I can say why one design needs fewer gates, and why a latch is a mistake.

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Worked in a real lab

Every lesson of this module is worked in a lab started for you alone. The labs it uses:

Teaching a class? Set this module for your students with a teacher guide, marked assignments and a lab for every student.