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Half adders and full adders

After this lesson: I can build a full adder from two half adders.

55 min lesson3 commandsDigital design lab: Verilog, VHDL and yosys on one private Ubuntu VM

How a chip adds two numbers

A binary adder is the circuit that adds two binary numbers. Every calculator and every processor has one.

It adds the way you add on paper: one column at a time, and a carry moves to the next column. Two small circuits, the half adder and the full adder, do that for one column.

By the end of this lesson

Note

I can build a full adder from two half adders.

Key words

WordWhat it meansExample
Sumthe bit that stays in the column
Carrythe bit that moves to the next column
Half adderadds two bits and gives a sum and a carry
Full adderadds two bits and a carry that came in
Carry inthe carry that arrives from the column on the rightcin
Overflowa result too big for the bits you have

The cells students fill in are left blank in this preview.

Binary addition works one column at a time

Add the bits in the right-hand column first. 1 + 1 is 2, which is 10 in binary. So the column keeps a 0 and sends a 1 to the left.

That 1 is the carry. The 0 that stays is the sum. The next column must add its own two bits and the carry that arrived.

Worked example: 101 plus 011

ColumnBits addedTotalSumCarry out
Right1 + 1 + 0 in201
Middle0 + 1 + 1 in201
Left1 + 0 + 1 in201
Extra bitNothing but the carry110

The cells students fill in are left blank in this preview.

A half adder is XOR plus AND

A half adder adds two bits. Its sum is a XOR b, because the sum is 1 when exactly one input is 1. Its carry is a AND b, because the carry is 1 only when both are 1.

It is called half because it has no place for a carry coming in. It can only do the right-hand column.

A half adder in Python

Code: python
# A half adder: two bits in, a sum bit and a carry bit out.
def half_add(a, b):
    return [a ^ b, a & b]

for a in [0, 1]:
    for b in [0, 1]:
        print(a, "+", b, "-> sum, carry =", half_add(a, b))
# Add a line that prints half_add(1, 1)[0] and half_add(1, 1)[1] on their own.

A full adder also takes the carry in

Every column except the first has a carry arriving. So its circuit adds three bits: a, b and the carry in. It gives a sum and a carry out.

A full adder can be built from two half adders and one more gate. Chain full adders, each carry out into the next carry in, and you can add numbers of any width.

Working out that last gate is the first task of the lab.

Verilog can add whole numbers with plus

You can also write x + y and let the tools build the adder. Here x and y are 4 bits wide and the answer has 5 bits.

The fifth bit is the carry out of the top column. Three Runs write a testbench, compile it and add 9 + 5 and then 15 + 1. The files go in /tmp.

Write the sum testbench

Command
echo 'module add_tb; reg [3:0] x, y; wire [4:0] total; assign total = x + y; initial begin x = 9; y = 5; #1 $display("%0d + %0d = %0d, binary %b", x, y, total, total); x = 15; y = 1; #1 $display("%0d + %0d = %0d, binary %b", x, y, total, total); end endmodule' > /tmp/add_tb.v

Shown here, not run. Create a free account to press Run and type it into your own lab’s terminal.

Compile it

Command
iverilog -o /tmp/add /tmp/add_tb.v

Shown here, not run. Create a free account to press Run and type it into your own lab’s terminal.

Run the simulation

Command
vvp /tmp/add

Shown here, not run. Create a free account to press Run and type it into your own lab’s terminal.

A common mistake

Warning

Many people think 15 + 1 on four bits gives 16. Four bits cannot hold 16. The top carry is lost, so the answer reads 0 unless you give the sum a fifth bit. Always ask how wide the answer must be.

About this lab and its source: Digital design lab: Verilog, VHDL and yosys on one private Ubuntu VM

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