A chip is described before it is built
A phone chip holds billions of switches. Nobody draws them one by one. An engineer writes the circuit as text in a hardware description language, and a program runs that text to see what the chip would do, long before anything is made.
By the end of this lesson
Note
I can simulate a small circuit written in Verilog and read the table and the waveform it gives.
Key words
- Module: one circuit, with inputs and outputs.
- Testbench: a module that drives another one and prints what comes out.
- Clock: a signal that rises and falls at a steady beat.
- Waveform: how signals change as time passes.
- Simulation: running the description on a computer.
Starter: what you already know
Note
Answer in your head. 1. What is 1 + 1 in binary? 2. What does an AND gate give for two 1s? 3. What is a bit? You need the first answer in a moment.
Before you start
Note
Press Start the lab on the bar at the top of this lesson. This lab is a whole Ubuntu machine of your own, so it takes a little longer to come up than a container. Each Run button types its command into the machine's terminal, one after another in the same session. If one says the machine is still starting, wait a few seconds and press it again. To watch them, or to type your own, press Open terminal on the bar.
A circuit is a short piece of text
Your files are in the folder hdl. The first command moves into it, and the next prints half_adder.v. A half adder adds two bits. It is one module with two inputs, a and b, and two outputs. sum is a ^ b, which is XOR, and carry is a & b, which is AND.
cd hdlShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
cat half_adder.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
A testbench runs it and prints the table
The tool is Icarus Verilog. iverilog compiles the circuit and its testbench into one program and prints nothing when it works. vvp runs that program. The testbench tries all four inputs and prints a truth table: the row 1 1 gives carry 1 and sum 0, which is 10 in binary, so 1 + 1 = 2.
iverilog -o /tmp/half half_adder.v half_adder_tb.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
vvp /tmp/halfShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Check
Tip
Which inputs make carry 1? Answer: only a = 1 and b = 1, the row where the sum is too big for one bit.
A common mistake
Warning
Many people think a Verilog file runs line by line, like a Python script. It does not. A module describes parts that all exist at the same moment, and an assign line is a wire that always follows its inputs. Read it as a drawing, not as a list of steps.
A clock and a waveform
counter.v is a 4-bit counter: q goes up by one every time clk rises, and rst sets it to 0. Its testbench makes a clock and records every signal in a VCD file, out/counter.vcd. The second Run prints q after 112 time units: 10. The third turns the file into text, one row for each signal and one column for each 5 time units. # is 1 and _ is 0. q stays 0 while rst is high, then goes up by one each time clk rises. dut.q is the same signal inside the counter.
iverilog -o /tmp/counter counter.v counter_tb.vShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
vvp /tmp/counterShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
vcd2txt out/counter.vcd 5Shown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Check
Tip
How many times did clk rise while q went from 0 to 10? Answer: ten, once for every step of the count.
The same circuit in VHDL
VHDL is the other common language. GHDL runs it in three steps. ghdl -a analyses the files and checks them. ghdl -e elaborates the testbench, which builds a program. ghdl -r runs it, and the testbench reports the four rows of the same truth table: a, b, carry and sum.
ghdl -a half_adder.vhd half_adder_tb.vhdShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
ghdl -e half_adder_tbShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
ghdl -r half_adder_tbShown here, not run. Create a free account to press Run and type it into your own lab’s terminal.
Exit check
Tip
Answer without looking back. 1. What does a testbench do? 2. What does vvp do? 3. What are the three GHDL steps? 4. What shows when a signal changes? Answers: drives a module and prints what comes out; runs the compiled simulation; analyse, elaborate, run; a waveform. Now open README.md in your home folder with cat ~/README.md: you write the full adder and the counter.
For teachers
Tip
This lesson is a small example of a lesson worked in a lab: the steps and the Run buttons are the lesson, and the lab is each student's own copy. This lesson is worked in a VM lab: each student has an Ubuntu machine of their own with the simulators installed, and a Run types into its terminal and shows what it printed. Key learning points: 1. A module is a circuit with inputs and outputs. 2. A testbench drives it and prints the truth table. 3. A clock makes a circuit change step by step, and a waveform shows it. Common mistake: reading Verilog as steps in order. Equipment: the lab and a browser. Tip: before the vvp Run, ask the class to predict the four rows. The lab itself has a check that marks three designs with hidden testbenches. Copy it into your own module and change it, or build one from scratch with the Lab menu in the lesson builder.